Verilog Digital Computer Design
Written by the co-developer of the Verilog Implicit To One hot (VITO) preprocessor, this text introduces the industry standard Verilog Hardware Description Language as a new way to explore enduring concepts in digital and computer design, such as pipelining. It shows how Verilog simulation is a tool for uncovering bugs prior to hardware fabrication, and how Verilog synthesis is a tool for automatically converting source code into hardware. Ideal for designers new to Verilog, it features a consistent design framework using ASM charts, and contains many realistic, practical examples.
Table of Content
- Why Verilog Computer Design?
- Designing ASMs.
- Verilog Hardware Description Language.
- Three Stages for Verilog Design.
- Advanced ASM Techniques.
- Designing for Speed and Cost.
- One Hot Designs.
- General-Purpose Computers.
- Pipelined General-Purpose Processor.
- RISC Processors.
- Machine and Assembly Language.
- PDP-8 Commands.
- Combinational Logic Building Blocks.
- Sequential Logic Building Blocks.
- Tri-State Devices.
- Tools and Resources.
- ARM Instructions.
- Another View on Non-blocking Assignment.
- Limitations on Mealy with Implicit Style.
Organizes coverage around design topics, such as pipelining, and emphasizes techniques that focus on creation of correct designs which reduce time to market.
Uses algorithmic state machines (ASMs) as the master plan in a top down approach — where physical details are ignored in order that the designer can concentrate on developing a correct algorithm.
Shows the correspondence of ASMs to implicit style Verilog — which is similar to software, except that the designer has control over scheduling of computation within clock cycles.
Fully discusses the relationships of the code to the cycle-by-cycle activity of the design.
Expresses designs with both ASM charts and Verilog.
Uses a few simple design examples of both special and general purpose machines to illustrate the tradeoff between hardware and software.
Offers extensive coverage of implicit style Verilog and non-blocking assignment — a high-level notation that captures, in an abstract way, the essential aspect of synchronous registers.
Features a novel ASM/Verilog description of pipelined and superscalar processors.
Contains a unique approach to one hot synthesis.